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Cyclicity Simulation Engine - Registration
Gavin J Stark
v0.01
April 20th 2004
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A module type registers with the simulation engine through the C++ API. It basically registers its name and an
instantiation callback (with handle), and then when the module type is instantiated the callback function is invoked.
This callback function can then check the options (parameters) which it is instantiated with, and declare its inputs and outputs.
The full details on this will be available within the API documentation
However, as an overview:
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A module instance should declare all its inputs and outputs.
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An input should be declared as 'used on a clock' if it is used to effect that clock edge. But this is not yet really necessary.
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An output should be declared as 'changing on clock' if it may change due to the clock edge. If in doubt, say it is. This will cause evaluation of combinatorial functions for other modules which use that signal unnecessarily at worst.
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An input should be declared as 'used combinatorially' if it may effect any of the outputs of the module combinatorially. The one caveat here is reset; it should be assumed for asynchronous reset that the reset signal is always removed just after a rising edge of the clock, and asserted just prior to the rising edge of the clock. Therefore it may be treated as a standard clocked input.
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An output should be declared as 'created combinatorially' if it is effected by any input combinatorially.
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A module instance may then only have one combinatorial function; all its combinatorial outputs are deemed valid at the end of execution of that function, and all its combinatorial inputs must be valid before it will be called.
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For submodule instantiations the scheduling and invocation of combinatorial, preclock and clock functions is the province of the main module instantiation functions. The submodules are, of course, registered with the simulation engine, but are instantiated explicitly by their parent as submodules through the main engine.
The parent module is expected to invoke:
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submodule_get_handle( submodule )
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submodule_get_clock_handle( submodule, clockname, &handle )
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if (has_edge(handle, posedge/negedge))
call_submodule_clock( handle, posedge/negedge )
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call_submodule_comb( submodule_handle )
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t_sl_error_level drive_submodule_input( submodule_handle, output, int*, size )
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int *get_submodule_output_driver( submodule_handle, output, int**, size )
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