Cyclicity CDL Documentation

Initially the documentation is a little sparse. It will fill out over time

Cyclicity CDL specification

CDL is the cycle description language that the Cyclicity suite utilizes as its top level design language. It is a high level design language for hardware description, with an emphasis on enforcing good design practice, readability, and verifiability. The languages is specified here. The CDL compiler has backends for C models for use in the simulation engine and for Verilog RTL, for synthesis with FPGA or ASIC tools or to run with Verilog simulators. There are a few known limitations of the current compiler (particularly the C model backend does not support arithmetic on buses wider than 32 bits, and reset values of arrays of types is under reexamination) but it is fine for most any use.

The unspecified/unimplemented feature list includes time-based assertions, which are a very good verification vehicle, and multithreaded operation. This work is underway.

Support library

The support library is released entirely free of any GPL or LGPL constraints. It has a number of very useful modules that are used throughout C models and the simulation engine.

Simulation engine

The simulation engine is a cycle-based simulation engine for C++ models. It can be coupled to a number of different harnesses, for batch simulation or GUI simulation. It links dynamically to C++ models of hardware modules, which may be instantiated by script files or by other harnesses. It simulates such instantiations of modules, and provides mechanisms for accessing their state, code coverage estimates, error and informational messages, and so on. It will in the future support checkpointing and restarting, such that simulations may be run through millions of cycles and then halted on error; the state, say, ten thousand cycles previously can have been checkpointed, and simulations restarted from that point to save much simulation time.