Cyclicity Simulation Engine

Gavin J Stark
April 20th 2004

Engine execution

The simulation harness is invoked from some simple execution harness; in particular here the code that is included in se_engine.cpp. This is to be moved in the near future to the new directory execution_harnesses/batch.cpp, where it can be placed under the GPL and dynamically linked to the simulation engine code.

This batch execution engine uses batch files written in the exec file language. As such is supports the standard exec file language, with some additional enhancements described below to support instantiation of individual simulations with arguments, and their execution.

Batch simulation exec file enhancements

Batch simulation exec files support the following commands, and also the waveform display (or rather, saving), code coverage and signal access simulation enhancements

read_hw_file(string filename)
discard the current instantiations, and read the given hardware file, which should be an instantiation exec_file
reset the current instantiations
step(integer cycles)
step the given number of cycles
setenv(string name, string value)
set an environment option for the hardware instantation file to read; this is the mechanism used for passing arguments to the instantiation files
display the state registered by the instantiations; useful for debugging

A simulation batch might then look like:

setenv "width" 16
setenv "module_name" hierarchy_test_harness
setenv "module_mif_filename" "hierarchy_test_harness.mif"
read_hw_file vector.hwex
step 50

This simulation file sets three arguments for the hardware instantiation, then reads a hardware instantiation batch file. It can then run a simulation (reset, step), before its work is completed.

The hardware instantiation file should have suitable test harnesses that produce pass and fail messges.

Additionally waveforms can be generated from a batch file, using the waveform exec file enhancements, for example like this (replacing the reset and step):

vcd_file_open hierarchy hierarchy.vcd
vcd_file_add  hierarchy vector_input_0 vector_input_1 vector_output_0 vector_output_1
vcd_file_enable hierarchy
step 50
vcd_file_close hierarchy

Furthermore, code coverage may be gathered for a simulation, or a module in the simulation, using the waveform exec file enhancements, for example like this (again replacing the reset and step):

coverage_load "coverage_file_so_far.cov"
step 50
coverage_save "coverage_file_so_far.cov"
This will build on a current code coverage file, so incremental code coverage can be performed

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