Cyclicity CDL

Cyclicity CDL is a cycle description language for hardware design, specifically for FPGA or silicon design, where a high level language is beneficial for the design.
This project contains a free implementation of the CDL language, which is capable of building C models and synthesizable verilog from a CDL description. The tools are released under three licenses most suitable to the code: the parser and code generators are released under the GPL; the simulation engine is released under the LGPL (in broad terms bascially because this engine is a library); some other support code is released as free code without any restrictions.
Nothing is released under a license more restrictive or prescriptive than the GPL.

Latest updates - Sept 2007

  • The simulation engine now supports a Python/gtk gui structure, with glade for its window descriptions.
  • The simulation engine now supports instantiation from within Cadence NC-Verilog with the VPI; the manner of instantiation seems somewhat esoteric, but it is quite functional (that's EDA languages for you, really, Cadence ones especially). Any cycle model that can be use with the cycle simulation can be used with Verilog, a great advance for test bench creation. It is also quite simple to use golden C models to compare hand-crafted Verilog or VHDL models, running them in parallel.
  • The support libraries have a new module sl_hier_mem, which supports hierarchical memories for us in simulation where a very large memory space is required but relatively little memory is actually used. A simple hierarchical page table is created dynamically as the memory is read and written (with optional allocate-on-read, obligatory allocate-on-write :-)), and the page table may be enumerated to ease checkpoint and restore. This type wil be added to the simulation engine in due course.
  • The simulation engine supports checkpoint and restore without, as yet, the chance for C models to register particular checkpoint and restore functions. The only data checkpointed and restored, currently, is the state declared to the simulation engine.


The first ever release (v0.01) of CDL occurred over the weekend of April 24th 2004. A second release (v0.02) took place on April 26th 2004; more of a drive for a standard build structure meant some changes required for releases. This release is quite functional; the CDL language is mostly implemented, and simulations can be run with VCD waveform generation, batch simulation, assertions, code coverage evaluation, hierarchical simulations, and so on.
Current releases are somewhat light on documentation; this work is underway, as and when it is required. For example, the tar file in the release does not actually include instructions for building it. But, to get you over that hurdle, those instructions are here

Release History

Date Version Comment
26th April 2004 v0.02 Improved some makefiles, pulled the batch mode execution harness out to give it a free license, made the simulation engine a real dynamic library, almost certainly broke cygwin builds in the process, added a synchronous SRAM internal module (untested as yet).
24th April 2004 v0.01 First release


There is some documentation (growing) in the documentation directory...
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